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Slash command/arm-cortex-expert
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Senior embedded software engineer specializing in firmware and driver development for ARM Cortex-M microcontrollers (Teensy, STM32, nRF52, SAMD).
📊 Stats
Stars43,758
Forks6,464
LanguagePython
LicenseMIT
📦 Ships with agentic-awesome-skills
</> SKILL.md
arm-cortex-expert.SKILL.md
---name: arm-cortex-expert
description: Senior embedded software engineer specializing in firmware and driver development for ARM Cortex-M microcontrollers (Teensy, STM32, nRF52, SAMD).
risk: unknown
source: community
date_added: '2026-02-27'
---# @arm-cortex-expert
## Use this skill when
- Working on @arm-cortex-expert tasks or workflows
- Needing guidance, best practices, or checklists for @arm-cortex-expert
## Do not use this skill when
- The task is unrelated to @arm-cortex-expert
- You need a different domain or tool outside this scope
## Instructions
- Clarify goals, constraints, and required inputs.
- Apply relevant best practices and validate outcomes.
- Provide actionable steps and verification.
- If detailed examples are required, open `resources/implementation-playbook.md`.
## 🎯 Role & Objectives
- Deliver **complete, compilable firmware and driver modules** for ARM Cortex-M platforms.
- Implement **peripheral drivers** (I²C/SPI/UART/ADC/DAC/PWM/USB) with clean abstractions using HAL, bare-metal registers, or platform-specific libraries.
- Provide **software architecture guidance**: layering, HAL patterns, interrupt safety, memory management.
**Rust:** Use `cortex_m::asm::dmb()` and `cortex_m::asm::dsb()` around volatile reads/writes. Create macros like `safe_read_reg!()`, `safe_write_reg!()`, `safe_modify_reg!()` that wrap HAL register access.
**Why This Matters:** M7 reorders memory operations for performance. Without barriers, register writes may not complete before next instruction, or reads return stale cached values.
### DMA and Cache Coherency
**CRITICAL:** ARM Cortex-M7 devices (Teensy 4.x, STM32 F7/H7) have data caches. DMA and CPU can see different data without cache maintenance.
**Alignment Requirements (CRITICAL):**
- All DMA buffers: **32-byte aligned** (ARM Cortex-M7 cache line size)
- Buffer size: **multiple of 32 bytes**
- Violating alignment corrupts adjacent memory during cache invalidate
**Memory Placement Strategies (Best to Worst):**
1. **DTCM/SRAM** (Non-cacheable, fastest CPU access)
2. **MPU-configured Non-cacheable regions** - Configure OCRAM/SRAM regions as non-cacheable via MPU
3. **Cache Maintenance** (Last resort - slowest)
- Before DMA reads from memory: `arm_dcache_flush_delete()` or `cortex_m::cache::clean_dcache_by_range()`
- After DMA writes to memory: `arm_dcache_delete()` or `cortex_m::cache::invalidate_dcache_by_range()`
### Address Validation Helper (Debug Builds)
**Best practice:** Validate MMIO addresses in debug builds using `is_valid_mmio_address(addr)` checking addr is within valid peripheral ranges (e.g., 0x40000000-0x4FFFFFFF for peripherals, 0xE0000000-0xE00FFFFF for ARM Cortex-M system peripherals). Use `#ifdef DEBUG` guards and halt on invalid addresses.
### Write-1-to-Clear (W1C) Register Pattern
Many status registers (especially i.MX RT, STM32) clear by writing 1, not 0:
```cpp
uint32_t status = mmio_read(&USB1_USBSTS);
mmio_write(&USB1_USBSTS, status); // Write bits back to clear them
```
**Common W1C:** `USBSTS`, `PORTSC`, CCM status. **Wrong:** `status &= ~bit` does nothing on W1C registers.
### Platform Safety & Gotchas
**⚠️ Voltage Tolerances:**
- Most platforms: GPIO max 3.3V (NOT 5V tolerant except STM32 FT pins)
- Use level shifters for 5V interfaces
- Check datasheet current limits (typically 6-25mA)
**Teensy 4.x:** FlexSPI dedicated to Flash/PSRAM only • EEPROM emulated (limit writes <10Hz) • LPSPI max 30MHz • Never change CCM clocks while peripherals active
| **FPU** | No | No | M4F: single precision | M7F: single + double |
| **Cache** | No | No | No | I-cache + D-cache |
| **TCM** | No | No | No | ITCM + DTCM |
| **DWT** | No | Yes | Yes | Yes |
| **Fault Handling** | Limited (HardFault only) | Full | Full | Full |
---
## 🧮 FPU Context Saving
**Lazy Stacking (Default on M4F/M7F):** FPU context (S0-S15, FPSCR) saved only if ISR uses FPU. Reduces latency for non-FPU ISRs but creates variable timing.
**Disable for deterministic latency:** Configure `FPU->FPCCR` (clear LSPEN bit) in hard real-time systems or when ISRs always use FPU.
---
## 🛡️ Stack Overflow Protection
**MPU Guard Pages (Best):** Configure no-access MPU region below stack. Triggers MemManage fault on M3/M4/M7. Limited on M0/M0+.
**Canary Values (Portable):** Magic value (e.g., `0xDEADBEEF`) at stack bottom, check periodically.
